Transmit clock generator

ABSTRACT

A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field,and more particularly, relates to a method of clock generation for atransmitter and a transmit clock generator.

DESCRIPTION OF THE RELATED ART

Integrated circuits forming a system-on-a-chip (SoC) typically utilizeserial links to provide chip-to-chip interconnects in high-speed networksystems. Such links often define a Front Side Bus (FSB) that includes aslower link layer that interfaces to a higher speed physical (PHY)layer. The PHY typically consists of a plurality of transmitter (Tx)cores that receive parallel data streams from the link layer andserially launch this data off-chip over the transmission media. Systemclocking is normally provided externally using a phase locked loop(PLL). A probable scenario would be to provide quarter rate clocks tothe link layer operating at 1.35 GHz and full rate clocks to the PHYoperating at 5.4 GHz. Since the same PLL provides both sets of clocksthe clocks are frequency synchronous but the phase relationship betweenthem is unknown.

As a result an asynchronous interface must first be handled before theparallel data sent from the FSB link layer can be reliably received bythe PHY Tx cores. This function is performed by the Tx clock generatorthat must create local phase synchronous versions of the quarter ratelink layer clock. These local clocks are then used to capture,serialize, and then transmit the data off-chip. In the scenariodescribed previously a local half rate clock operating at 2.7 GHz andphase synchronous to the full rate PHY clock captures incoming data. Anadditional local phase synchronous quarter rate clock assists in theserialization and the data is then transmitted using both transitions ofthe previous local half rate clock, producing a serial data rate of 5.4Gbps across the link. Disadvantages of conventional arrangements forcreating these local phase synchronous clocks include the inherentcircuit complexity required for generating multiple waveform sets forphase synchronization and for generating training sequences. Suchconventional arrangements require excessive hardware for dual waveformconstruction and associated multiplexing and control, and for trainingclosure.

A need exists for an improved transmitter (Tx) clock generationtechnique for creating the local phase synchronous clocks required tocapture, serialize, and transmit the incoming parallel data from the FSBlink layer.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method ofclock generation for a transmitter and a transmit clock generator. Otherimportant aspects of the present invention are to provide such method ofclock generation for a transmitter and a transmit clock generatorsubstantially without negative effect and that overcome many of thedisadvantages of prior art arrangements.

In brief, a transmit clock generator and a method of clock generationfor a transmitter are provided. A first local clock generator and asecond local clock generator receiving an external PLL clock signal andrespectively generating first and second divided clock signals. Asynchronization signal is applied to the first local clock generator andsecond local clock generator during a clock training period to enforce aphase relationship between the first and second divided clock signals.The synchronization signal includes at least one synchronization pulsethat is applied to the first local clock generator and second localclock generator during the clock training period.

In accordance with features of the invention, the synchronization signalis generated using a data clock sampler that receives and samples a datasynchronous clock signal, referred to as data_sample, that is derivedfrom a link layer clock, and sampled by the external full rate PLLclock. Sample outputs of the data clock sampler are applied to asynchronization pulse generator that detects rising edge samples fromthe data clock sampler and outputs rising edge synchronization pulses. Agated synchronization repower tree repowers the rising edgesynchronization pulses. A synchronization control signal generated by aclock synchronization control gates the gated synchronization repowertree to allow at least one synchronization pulse to be applied to thefirst local clock generator and second local clock generator only duringthe clock training period.

In accordance with features of the invention, the clock training periodis established by the clock synchronization control responsive to anapplied reset signal indicating proper power to the transmitter has beenestablished and no reset conditions are pending and an applied inputindicating valid synchronization pulses are being produced.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above and other objects andadvantages may best be understood from the following detaileddescription of the preferred embodiments of the invention illustrated inthe drawings, wherein:

FIG. 1 is a block diagram illustrating an exemplary transmit clockgenerator in accordance with the preferred embodiment;

FIG. 2 illustrates an exemplary clock initialization/reset functionalblock of the exemplary transmit clock generator of FIG. 1 in accordancewith the preferred embodiment;

FIG. 3 illustrates an exemplary clock synchronization control functionalblock of the exemplary transmit clock generator of FIG. 1 in accordancewith the preferred embodiment;

FIG. 4 illustrates an exemplary data clock sampler functional block ofthe exemplary transmit clock generator of FIG. 1 in accordance with thepreferred embodiment;

FIG. 5 illustrates an exemplary synchronization pulse generatorfunctional block of the exemplary transmit clock generator of FIG. 1 inaccordance with the preferred embodiment;

FIG. 6 illustrates an exemplary gated synchronization repower treefunctional block of the exemplary transmit clock generator of FIG. 1 inaccordance with the preferred embodiment;

FIG. 7 illustrates an exemplary half rate local 2.7 GHz clock generatorfunctional block of the exemplary transmit clock generator of FIG. 1 inaccordance with the preferred embodiment; and

FIG. 8 illustrates an exemplary quarter rate local 1.35 GHz clockgenerator functional block of the exemplary transmit clock generator ofFIG. 1 in accordance with the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Having reference now to the drawings, in FIG. 1, there is shown anexemplary transmit clock generator generally designated by the referencecharacter 100 in accordance with the preferred embodiment. Transmitclock generator 100 is illustrated and described for a link layer datarate of 1.35 GHz (¼×) and a sampling data rate of 5.4 GHz (1×); however,it should be understood that principles of the present invention areapplicable to various other link layer and sampling data rates.

In accordance with features of the transmit clock generator of thepreferred embodiment, advantages include: 1) Robustness, the new methodof clock generation implemented by transmit clock generator 100 isinsensitive to the duty cycle of the DATA_SAMPLE clock, such as a FrontSide Bus (FSB) 1.35 GHz link layer clock and provides an enhanced anddependable training closure scheme. 2) Simplicity, the new method ofclock generation requires less hardware than conventional arrangementssince it avoids dual waveform construction and associated multiplexingand control, and simpler training closure hardware. 3) Flexibility, thenew method of clock generation enables the use a wider range ofDATA_SAMPLE frequencies. 4) Extendibility, the new method of clockgeneration easily supports additional levels of serialization by addingadditional local clock generators, sharing common synchronizationsignals.

In accordance with features of the preferred embodiment, clocksynchronization is provided within a narrow time window, or trainingperiod, during system power on. Transmit clock generator 100 samples anincoming clock, with frequency ¼× (1.35 GHz) and phase y, with asampling clock of frequency 1× (5.4 GHz) and a phase z, once each cycleof the sampling clock. The incoming clock, shown as DATA_SAMPLE in FIG.1, is sampled at both its high value and low value provided the samplingdoes not occur during a rising or falling transition which could fall inthe metastable region of the sampling clock. However, if the samplingdoes occur within the metastable region of the sampling clock thissample is still retained since the new transition value has been eitherjust captured or just missed. If the new transition value was justmissed, a new transition value will be captured in the next cycle of thesampling clock so that the sampling accuracy is within one cycle of thesampling clock. In the transmit clock generator 100 metastability isresolved by double latching the sampled waveforms, as shown in FIG. 4using an L1L2 latch pair.

In accordance with features of the preferred embodiment, transmit clockgenerator 100 performs a rising edge detect on the incoming clock and sois insensitive to its duty cycle. Transmit clock generator 100 does notrely upon repetitive periodic waveforms to produce reliable local clocksand avoids the use of multiple data clock samplers which guard againstmaking clock synchronization decisions based on potentially metastablesampling of the DATA_SAMPLE clock. Such conventional schemes oftenrequire additional hardware to produce multiple chains of samplinglatches, delay elements, comparison logic, and the extra multiplexingneeded to select proper DATA_SAMPLE clock samples for clocksynchronization. Transmit clock generator 100 only relies on rising edgetransitions of the incoming DATA_SAMPLE and since it needs only onevalid synchronization pulse to train the local clock generators, it iscapable of using an incoming DATA_SAMPLE at the ¼× frequency or afrequency that has been divided down, say ⅛× or 1/16×.

As shown in FIG. 1, the transmit clock generator 100 includes multiplefunctional blocks including a Clock Initialization/Reset 102, a ClockSynchronization Control 104, a Data Clock Sampler 106, a SynchronizationPulse Generator 108, a Gated Synchronization Repower Tree 110, a Local2.7 GHz Clock Generator 112, and a Local 1.35 GHz Clock Generator 114.

A power good signal PGOOD and a transmit reset signal TX_RESET areapplied to the Clock Initialization/Reset 102, which generates an outputreset signal RESET_B. Until the Clock Initialization/Reset 102 receivesan active PGOOD signal or as long as there is a pending TX_RESET,transmit clock generator 100 remains in a synchronization mode and willtrain the local serialization clocks 112, 114, synchronizing the localserialization clocks with applied differential 5.4 GHz PLL clock inputsthat are generated external to the transmit clock generator 100. Thiscondition forces the output of the Clock Initialization/Reset 102,RESET_B, to be low. When an active PGOOD signal is received and whenthere is no outstanding TX_RESET then the output of the ClockInitialization/Reset 102, RESET_B, goes high.

As shown in FIG. 1, the Clock Synchronization Control 104 receives theoutput of the Clock Initialization/Reset 102, RESET_B and an outputN_SYNC of the Synchronization Pulse Generator 108 and generates anoutput signal CLOSE_LOOP that indicates when the clock synchronizationloop is able to be closed. Clock Synchronization Control 104 is used todetermine whether the transmit clock generator 100 needs to continuesampling the DATA_SAMPLE clock using Data Clock Sampler 106 to generatesynchronization pulses to train the Local 2.7 GHz (½×) Clock Generator112 and the Local 1.35 GHz (¼×) Clock Generator 114 or whether theselocal clocks have already been properly synchronized.

The output signal RESET_B from the Clock Initialization/Reset 102indicates that proper power has been established and that no resetconditions are pending. The output signal N_SYNC from theSynchronization Pulse Generator 108 indicates that valid synchronizationpulses are being produced. This information is used to generate theoutput signal CLOSE_LOOP that is applied to the Gated SynchronizationRepower Tree 110 which generates synchronization pulses applied to theLocal 2.7 GHz (½×) Clock Generator 112 and the Local 1.35 GHz (¼×) ClockGenerator 114.

The Synchronization Pulse Generator 108 is responsive to the rising edgesamples of the DATA_SAMPLE and, when detected, outputs latched,active-high sync pulses via the Gated Synchronization Repower Tree 110that are 1 unit-interval (UI) in duration, where a UI is defined as theperiod of the 5.4 GHz clock. These sync pulses SYNC serve two purposes,to synchronize clocks to be used to capture, serialize, and transmit thelink layer data and handshaking to indicate that synchronization hasbeen completed. Properly serializing the raw link layer data requiresthat the frequency dividers indicated in the Local 2.7 GHz ClockGenerator 112 and the Local 1.35 GHz Clock Generator 114 are not onlyfrequency synchronous with the local 5.4 GHz PLL clocks but also phasedeterminate. The Sync Pulse Generator 108 via the Gated SynchronizationRepower Tree 110 feeds these dividers of the Local 2.7 GHz ClockGenerator 112 and the Local 1.35 GHz Clock Generator 114 and forces therequired phase relationships, possibly overriding previously establishedrelationships.

When the output signal CLOSE_LOOP indicates that the clocksynchronization loop is still open, synchronization pulses are sent tothe Local 2.7 GHz (½×) Clock Generator 112 and the Local 1.35 GHz (¼×)Clock Generator 114 to force these local clock generators that arealready frequency synchronous with the 5.4 GHz PLL clock inputs to alsobe phase determinate. The phase relationship between the Local 2.7 GHzClock Generator 112 and the Local 1.35 GHz Clock Generator 114 isimportant to properly serialize the parallel data received from the FSBlink layer. The clocks of the Local 2.7 GHz Clock Generator 112 and theLocal 1.35 GHz Clock Generator 114 are generated using frequencydividers, clocked by the 5.4 GHz PLL clocks, as illustrated anddescribed with respect to FIGS. 7 and 8.

Referring now to FIG. 2, there is shown an exemplary clockinitialization/reset functional block 102 of the transmit clockgenerator 100 in accordance with the preferred embodiment. ClockInitialization/Reset functional block 102 is formed by a level shifter202 receiving the PGOOD signal and coupled by a first L1L2 latch pair204 and a second L1L2 latch pair 206 to a first input of a two input ANDgate 208. The TX_RESET signal is applied to a level shifter 210 andcoupled by a first L1L2 latch pair 212 and a second L1L2 latch pair 214to a second inverting input of the two input AND gate 208. Externallygenerated differential 5.4 GHz PLL clock inputs labeled L54_N, L54_P areapplied to respective clock inputs of the L1L2 latch pairs 204, 206,212, 214. The AND gate 208 provides the output signal RESET_B of theClock Initialization/Reset 102. The level shifters 202 and 210optionally are provided for voltage level shifting where needed when thelink layer and physical layer have different voltage domains. The PGOODsignal is applied to the L1L2 latch pair 204 and similarly the TX_RESETsignal is applied to the L1L2 latch pair 212, when the optional levelshifters 202 and 210 are eliminated.

Referring now to FIG. 3, there is shown an exemplary ClockSynchronization Control functional block 104 of the transmit clockgenerator 100 in accordance with the preferred embodiment. ClockSynchronization Control 104 is formed by a two input OR gate 302 coupledto a two input AND gate 304 coupled to an L1L2 latch pair 306 providingthe output signal CLOSE_LOOP. OR gate 302 receives the N_SYNC output ofthe Synchronization Pulse Generator 108 and feedback of the generatedoutput signal CLOSE_LOOP. AND gate 304 receives the output of OR gate302 and the output signal RESET_B from the Clock Initialization/Reset102. The output of AND gate 304 is applied to the L1 latch of the L1L2latch pair 306. The externally generated differential 5.4 GHz PLL clockinputs L54_N, L54_P are applied to respective clock inputs of the L1L2latch pair 306 that provides the output signal CLOSE_LOOP at the L2latch output.

Referring now to FIG. 4, there is shown an exemplary Data Clock Samplerfunctional block 106 of the transmit clock generator 100 in accordancewith the preferred embodiment. Data Clock Sampler 106 includes aplurality of series connected L1L2 latch pairs 402, 404, 406, 408, eachclocked at the externally generated differential 5.4 GHz PLL clockinputs.

A clock input, derived from the link layer clock and sharing the sametiming relationship with respect to the link layer clock as the raw,unserialized link layer data, shown as DATA_SAMPLE, is applied as aninput to the Data Clock Sampler 106 to the master L1 latch of the firstlatch pair 402. The Data Clock Sampler 106 also receives a frequencysynchronous sampling clock, which is for example, a repowered copy ofthe external differential 5.4 GHz PLL clock. The sampled DATA_SAMPLE, atthe NCP2 output of L1L2 latch pair 406 and the NCP3 output of L1L2 latchpair 408, is directed to the Synchronization Pulse Generator 108, whichperforms a rising edge detection.

During a training period the Data Clock Sampler 106 performs a 4× orgreater over-sampling of the 1.35 GHz or slower DATA_SAMPLE input clockusing a sampling latch clocked at 5.4 GHz. Since the DATA_SAMPLE inputshares the same timing relationships as the raw data received from thelink layer, this is equivalent to actually sampling the raw data itselfand creating synchronous clocks that will be used to capture, serialize,and transmit the raw data in the Tx first-in first-out registers (FIFOs)and drivers (not shown). The sampling L1 latch of the Data Clock Sampler106 is the first L1 (master) sampling latch of latch pair 402 thatcaptures the DATA_SAMPLE input. The remaining latches L2 of the firstlatch pair 402, and L1L2 latch pairs 404, 406, 408 are used inpipelining the samples and to filter out any metastable effectsresulting when the asynchronous DATA_SAMPLE input arrives in themetastable region of the L1 sampling latch. To eliminate sensitivity tothe duty cycle of the link layer clock, the only samples of interest arein the region of rising DATA_SAMPLE transitions, correspondingly risinglink layer clock transitions, which signal the beginning and subsequentend of a raw data cycle. If the rising DATA_SAMPLE edge occurs withinthe metastable region of the L1 sampling latch 402 the value of thesample is indeterminate and this leads to a quantization error of atmost 1 UI. Since the raw data cycle itself is only 4 UI wide, this 1 UIquantization error needs to be accounted for in balancing the overallsetup and hold margins when latching the raw data to be serialized inthe Tx FIFOs.

Referring now to FIG. 5, there is shown an exemplary SynchronizationPulse Generator functional block 108 of the transmit clock generator 100in accordance with the preferred embodiment. Synchronization PulseGenerator 108 includes a two input AND gate 502 that receives the NCP2output of L1L2 latch pair 406 and receives and inverts the NCP3 outputof L1L2 latch pair 408 of the Data Clock Sampler 106. The ANDED outputsNCP2 and inverted NCP3 provide the N_SYNC of the Synchronization PulseGenerator 108.

Referring now to FIG. 6, there is shown an exemplary GatedSynchronization Repower Tree functional block 110 of the transmit clockgenerator 100 in accordance with the preferred embodiment. GatedSynchronization Repower Tree 110 includes a two input AND gate 602receiving the N_SYNC of the Synchronization Pulse Generator 108 andreceiving and inverting the CLOSE_LOOP output of the ClockSynchronization Control 104 that together define the synchronizationtraining period. The ANDED outputs N_SYNC and inverted CLOSE_LOOPprovide the SYNC pulse output of AND gate 602 that is applied to thelocal clock generators 112 and 114.

The rising edge synchronization pulses N_SYNC output of theSynchronization Pulse Generator 108 are then repowered in the GatedSynchronization Repower Tree 110, where they are also gated by asynchronization control signal output CLOSE_LOOP, provided by the ClockSynchronization Control 104, that only allows synchronization pulses tobe sent to the local clock generation blocks 112, 114 if the clocksynchronization loop is open.

When an active PGOOD signal is received and when there is no outstandingTX_RESET the first sync pulse N_SYNC sent to the Clock Sync Control 104under these conditions activates the CLOSE_LOOP control signal that willgate off the Gated Synchronization Repower Tree 110, preventingsubsequent SYNC pulses from being generated. The control loop terminatesthe training based upon valid power, the absence of any Tx resets, andthe receipt of at least one valid synchronization pulse. This keeps the2.7 GHz and 1.35 GHz frequency dividers of the local clock generators112 and 114 in a free running state where they retain the phaserelationships dictated by the last received sync pulse during thetraining period.

FIG. 7 illustrates an exemplary Local 2.7 GHz Clock Generator functionalblock 112 of the transmit clock generator 100 in accordance with thepreferred embodiment. Local 2.7 GHz Clock Generator 112 includes afrequency divider defined by a multiplexer 702 used for testing coupledto a two input OR gate 704 coupled to an L1L2 latch pair 706 with theclock output labeled LCLK27_P of the L2 latch fed back to a first inputof multiplexer 702. The SYNC output of the Gated Synchronization RepowerTree 110 is applied to an input of OR gate 704. The externaldifferential 5.4 GHz PLL clock drives the L1L2 latch pair 706 thatcreate the half rate frequency or 2.7 GHz output LCLK27_P.

FIG. 8 illustrates an exemplary Local 1.35 GHz Clock Generatorfunctional block of the transmit clock generator 100 in accordance withthe preferred embodiment. Local 1.35 GHz Clock Generator 114 includes afrequency divider defined by a multiplexer 802 used for testing coupledto a first two input OR gate 804 coupled to an L1L2 latch pair 806. TheL1L2 latch pair 806 is coupled to a second two input OR gate 808 coupledto an L1L2 latch pair 810 with the clock output labeled LCLK135_P of theL2 latch fed back to a first input of multiplexer 802. The SYNC outputof the Gated Synchronization Repower Tree 110 is applied to an input ofthe OR gates 804, 808. The external differential 5.4 GHz PLL clockdrives the L1L2 latch pairs 806, 810 that create the quarter ratefrequency or 1.35 GHz output LCLK135_P.

While the present invention has been described with reference to thedetails of the embodiments of the invention shown in the drawing, thesedetails are not intended to limit the scope of the invention as claimedin the appended claims.

1-4. (canceled)
 5. A transmit clock generator for clock generation for atransmitter comprising: a first local clock generator and a second localclock generator, each receiving an external PLL clock signal andrespectively generating first and second divided clock signals; asynchronization signal for enforcing a phase relationship between thefirst and second divided clock signals; said synchronization signalbeing applied to said first local clock generator and said second localclock generator during a clock training period; said synchronizationsignal including at least one synchronization pulse being applied to thefirst local clock generator and second local clock generator during theclock training period; and a data clock sampler for generating saidsynchronization signal; said data clock sampler receiving and sampling adata synchronous clock signal for providing sample outputs, and saiddata clock sampler being clocked by the external PLL clock; said dataclock sampler including a first master latch receiving said datasynchronous clock signal and a first slave latch coupled to said masterlatch, said first master and first slave latches being connected to asecond master and second slave latch for resolving metastability bydouble latching sampled data clock inputs; and a plurality of latchesbeing series connected to said master and slave latches for pipeliningsample outputs.
 6. (canceled)
 7. A transmit clock generator for clockgeneration for a transmitter comprising: a first local clock generatorand a second local clock generator, each receiving an external PLL clocksignal and respectively generating first and second divided clocksignals; a synchronization signal for enforcing a phase relationshipbetween the first and second divided clock signals; said synchronizationsignal being applied to said first local clock generator and said secondlocal clock generator during a clock training period; saidsynchronization signal including at least one synchronization pulsebeing applied to the first local clock generator and second local clockgenerator during the clock training period; and a data clock sampler forgenerating said synchronization signal; said data clock samplerreceiving and sampling a data synchronous clock signal for providingsample outputs, and said data clock sampler being clocked by theexternal PLL clock; said sample outputs of the data clock sampler beingapplied to a synchronization pulse generator; said synchronization pulsegenerator for generating synchronization pulses; said synchronizationpulse generator detecting rising edge samples from the data clocksampler and outputs rising edge synchronization pulses.
 8. A transmitclock generator as recited in claim 7 includes a gated synchronizationrepower tree, and said gated synchronization repower tree receiving andrepowering said rising edge synchronization pulses.
 9. A transmit clockgenerator as recited in claim 8 wherein said gated synchronizationrepower tree is gated by a synchronization control signal generated by aclock synchronization control; said synchronization control signal forallowing at least one synchronization pulse to be applied to the firstlocal clock generator and second local clock generator only during theclock training period.
 10. A transmit clock generator as recited inclaim 9 wherein said clock synchronization control establishes the clocktraining period responsive to an applied reset signal indicating properpower to the transmitter has been established and no reset conditionsare pending and an applied input indicating valid synchronization pulsesare being produced.
 11. A transmit clock generator as recited in claim 9wherein said clock synchronization control includes an OR gate receivingsaid synchronization pulses and feedback of the synchronization controlsignal; said OR gate coupled to an input of an AND gate and a resetsignal applied to another input of said AND gate, said AND gate coupledto a first latch of a latch pair; said latch pair providing thesynchronization control signal, said external PLL clock signal appliedto respective clock inputs of said latch pair.
 12. A transmit clockgenerator as recited in claim 11 wherein said reset signal is generatedby a clock initialization and reset functional block; said clockinitialization and reset functional block receiving a power good signaland a transmitter reset signal; said clock initialization and resetfunctional block including an AND gate for combining said receivedsignals.
 13. A transmit clock generator as recited in claim 6 whereinsaid synchronization pulse generator includes an AND gate receivingsample outputs of a first pipelined latch pair and receiving sampleoutputs of a second pipelined latch pair of said data clock sampler. 14.A transmit clock generator as recited in claim 9 wherein said gatedsynchronization repower tree includes an AND gate having an inputreceiving said synchronization control signal and an input receivingsaid rising edge synchronization pulses. 15-19. (canceled)